1. Field of the Invention
The present invention relates generally to electronic imaging sensors and, specifically, to advanced imaging system-on-chip (iSoC) sensors having embedded signal processing functions.
2. Description of the Related Art
Imaging sensors operate by collecting light intensity in a contiguous array of imaging pixels. Each pixel will have a charge proportional to the intensity of the light incident on the pixel over the duration of exposure. This charge is a “pixel value” that must be read out with as little noise as possible to capture a high quality image or generate video. Although modem CMOS sensors have lower temporal noise than CCD imaging sensors at data rate >25 MHz, several sources of systematic artifacts can degrade image quality, especially at low illumination.
Readout of the image electronically reproduced in CMOS imaging sensors is achieved by routing the signal from each row of pixels through a set of column buffers to the output as shown in FIG. 1 from U.S. Pat. No. 6,861,634. Each column buffer 102 normally supports a specific column of pixels and is constructed using an integrated amplifier block such as taught in U.S. Pat. No. 5,892,540. Although circuit block 70 in FIG. 2 from '540 corrects column buffer offsets in the analog domain to about 100 μV rms as compared to a full-scale signal on the order of 1V, i.e., one part in 104, maximizing image quality mandates further reducing “column noise.” Likewise, because each video line is read at a different time than either the prior or next line, the readout process can introduce “line noise.” Furthermore, the supporting column buffers use common reference voltages (such as REF1, REF2 and REF3 in FIG. 2) that carry intrinsic noise with time-varying characteristics. Since each row of pixels is sampled at the same time, each row of pixels samples the common reference noise at similar aggregate value. On the other hand, subsequent rows are interrogated at different times and thus sample the common references at slightly different collective values. This row-to-row variability generates “line noise” and frame-to-frame “flicker.” All these possible noise mechanisms degrade image quality via the following deleterious effects:    1. Vertical stripes that are set and can dynamically fluctuate on a column-to-column basis.    2. Horizontal stripes that are set and can dynamically fluctuate on a line-to-line basis, i.e., line noise wherein each line is a horizontal stripe of pixels.    3. Frame-to-frame instability that is a by-product of an image sensor's sensitivity to reference noise. The sensitivity effectively destabilizes the sensor's black level on a frame-by-frame basis since vertical blanking time is significantly longer than horizontal blanking time. Hence, black reference behavior is strongly frame-dependent.In high performance imaging sensors, the most distracting effect is frame-to-frame instability.
In the prior art, U.S. Pat. No. 5,172,249 subtracts amplifier offsets and FPN by applying signal and reference levels to the input of a subtraction circuit, such as a differential amplifier, without due consideration for the deleterious impact of wideband noise in causing offset correction errors. U.S. Pat. No. 6,037,577 alternatively provides means to suppress row noise on a row-by-row basis. However, the primary intent is again to suppress offsets from switching noise and charge redistribution among the parallel signal paths rather than to eliminate discretely sampled common reference noise.
U.S. Pat. No. 6,861,634 subsequently teaches a technique for subtracting reference noise in addition to other sources of sensor noise. The noise subtraction is performed in the analog domain using a correction value previously determined in the digital domain. The analog value is supplied to a sample-and-hold circuit including a charge amplifier for subtracting the offset. The preferred embodiment teaches pseudo-differential or differential signal paths using the pixel's signal level and associated reset level. Unfortunately, burdening the signal path by also supplying the reset level to the offset-subtracting amplifier halves the maximum video rate, doubles the concomitant video bandwidth, and boosts white noise. The correction is also carried out at high speed on a pixel-by-pixel and per-color basis, thus increasing complexity and signal processing overhead.
Recently, U.S. Patent Application Publication No. 2006/0231734 teaches wholly digital means to determine and correct column fixed pattern noise. This effectively limits accuracy of the various corrections rather than enhancing the analog dynamic range presented for A/D conversion.